HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 6. Loopback Interface Diagram
Data In
OE0, OE1
S2042
Fibre
Channel
Transmitter
S2043
Fibre
Channel
Receiver
Data Out
CLK
S2042/S2043
Table 4. Receiver Operating Modes
Reference
Clock RCLK/RCLKN
Word
Data Rate Width Frequency Frequency
(MHz)
(MHz)
RATESEL DWS REFSEL (Mbits/sec) (Bits)
0
0
1
0
1
0
1
1
0
1
0
1
1062.5
1062.5
531.25
531.25
265.625
10
20
10
20
10
106.25
53.125
53.125
26.5625
26.5625
53.125
53.125
53.125
26.5625
26.5625
Local
Loopback
Local
Loopback
1
1
Open
Data Out
CLK
S2043
Fibre
Channel
Receiver
S2042
Fibre
Channel
Transmitter
Data In
OE0, OE1
Start-Up Procedure
The clock recovery PLL requires an initilization proce-
dure to correctly achieve lock on the serial data inputs.
At power-up or loss of lock, the PLL must first acquire
frequency lock to the local reference clock. This can be
accomplished in three ways: 1) The –LOCK_REF pin
can be connected to a 10 ms reset signal to initialize
the PLL. 2) By guaranteeing that no data is seen at the
serial data inputs for a minimum of 10 ms upon power-
up. 3) The S2043 can be put into the loopback mode
and the loopback outputs of the S2042 must be quies-
cent for a minimum of 10 ms after power-up.
Other Operating Modes
Loopback
Local loopback requires a S2042 and a S2043 as shown
in the Figure 6. When enabled, serial data from the
S2042 transmitter is sent to the S2043 receiver, where
the clock is extracted and the data is deserialized. The
parallel data is then sent to the subsystem for verifica-
tion. This loopback mode provides the capability to
perform offline testing of the interface to guarantee the
integrity of the serial channel before enabling the trans-
mission medium. It also allows system diagnostics.
Operating Frequency Range
The S2042 and S2043 are optimized for operation at
the Fibre Channel rates of 266, 531 and 1062 Mbit/s.
Operation at other than Fibre channel rates is pos-
sible if the rate falls within
±10%
of the nominal rate.
REFCLK must be selected to be within 100 ppm of
the desired byte or word clock rate.
Test Modes
The TEST pin on the S2042 and the SYNCEN pin on
the S2043 provide a PLL bypass mode that can be
used for operating the digital area of the chip. In this
mode, clock signals are input through the reference
clock pins. This can be used for testing the device
during the manufacturing process or during an off-
line self-test. Sync detection is always enabled in
test mode.
When framing is disabled by low SYNCEN, the S2043
simply achieves bit synchronization within 250 bit times
and begins to deliver parallel output data words whenever
it has received full transmission words. No attempt is made
to synchronize on any particular incoming character. The
SYNCEN input should be static during operation (i.e.
connected to VCC or GND). The S2043 will not main-
tain the existing byte synchronization when SYNCEN
transitions from the active to inactive state.
The SYNC output signal will go high whenever a
K28.5 character (positive disparity) is present on the
parallel data outputs. The SYNC output signal will be
low at all other times. This is true whether the S2043
is operating in 10-bit mode or in 20-bit mode. In 20-
bit mode, the K28.5 byte will always be placed in the
MSB (D0-D9). In 10-bit mode, the K28.5 will be
clocked with the RCLKN output.
Lock Detect
The S2043 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock within 250 bit times after the
start of receiving serial data inputs. If the serial data
inputs have an instantaneous phase jump (from a
serial switch, for example) the PLL will not indicate
an out-of-lock state, but will recover the correct phase
alignment within 250 bit times. If a run length of 64
bits is exceeded, or if the transition density is less
than 12%, the loop will be declared out of lock and
will attempt to re-acquire bit synchronization. When
lock is lost, the PLL will shift from the serial input
data to the reference clock, so that correct frequency
downstream clocking will be maintained.
In any transfer of PLL control from the serial data to
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
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