S2024
OPERATING MODES
SYNCHRONOUS MODE
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
Figure 2. Synchronous Mode
t
SUDI
DINØ–31
A
MC
MPWH
t
HDI
B
MC
MPWL
C
In synchronous mode, two clock signals, MDCLK for
data input and SDCLK for data output, provide the latch
enable strobes to allow the input data and output data
to be stored in 32-bit latches. The S2024 is capable of
400-Mbit/s operation in this mode. The data is latched
on the falling edge of SDCLK and MDCLK.
Inputs MDCLK/MDCLKN and SDCLK/SDCLKN can be
used as true differentials or as single-ended clocking
signals. Onboard voltage reference outputs VBB1 and
VBB2 allow single-ended clocking capability when con-
figured as shown in Figure 8.
TRANSPARENT MODE
In transparent, or asynchronous, mode, any data ap-
pearing at the input will be passed immediately through
to its designated output. Transparent transfer of data
through the latches takes place when both MDCLK and
SDCLK clock inputs are held high. In this mode the
S2024 is capable of up to a 800 Mbit/s NRZ data rate.
RECONFIGURATION MODE
The S2024 can be selectively reconfigured one output
at a time, or any number of outputs can be reconfigured
simultaneously. Configuration data is stored in 32 registers,
one register for each output data pin. The 6-bit content
of each register selects the input data pin which is to be
connected to that output data pin. To connect an output
to a given input, the output to reconfigure is selected
using OUTADD0–4 and OAEN to enable the appropriate
output configuration register. With the output configura-
tion register selected, the desired input pin connection
is provided on INADD0–5. The input pin selection on
INADD0–5 will be stored into the selected output con-
figuration register on the rising edge of CNFGCLK.
When the switch is to be reconfigured, the S2024 mini-
mizes the time required through the use of an additional
configuration latch. While the switch is operational (and
prior to the time at which it must be reconfigured) a new
set of input addresses can be loaded into the register
file. When all registers have been updated, the contents
of the registers are parallel-transferred to the configura-
tion latch, when CNFGSTB goes high. This process
allows a switch reconfiguration in just 4 ns.
MDCLK/N
t
OVRL
SDCLK/N
t
SUXDI
t
HXDI
XDINØ–31
A
t
SCKDO
B
DOUTØ–31
A
B
Figure 3. Transparent Mode
DI
MPW
DINØ–31
A
B
C
D
E
t
DIDO
DOUTØ–31
A
t
XIDO
CNFGSTB
XI
MPW
XINØ–31
A
B
C
B
C
t
CFDO
D
E
D
E
Figure 4. Reconfiguration Mode
t
SUOA
OUTADDØ–4
ADDRESS VALID
t
SUOAE
OAEN
t
SUIA
INADDØ–5
t
HIA
t
HOAE
t
HOA
VALID
CC
MPWL
CC
MPWH
CNFGCLK
CS
MPWH
t
SUCFC
CNFGSTB
2
June 15, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
