HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
{WAITPKT} The WAIT PacKeT state is entered when
HOST DATA/FIFO SM INTERNAL STATES
there is no active Packet and the decode of “DRDY” is
true, indicating that both BSTAV and DATAV were
asserted from the Source Host system.
The defined states are as follows:
{INIT} The INITialization state is the entry point of the
Host Data/FIFO SM. This state is unconditionally
entered by a “RST” decode of the inputs. The state
is also entered by a “DSCN” decode representing
the disconnected state of the HIPPI channel. This
state remains active if a “CNRQ” decode is true
while the “NODT” decode remains false, indicating
a Connection request without Data available from
the FIFO. The state is exited to the {RDIFL} state
by the decode of “CNRQ” and “DTAV” both true.
The decode of “CON” in this state is a Destination
error and the {DESTERR} state is entered.
This state will read one word from the Source Host
FIFO. If the “NPIF” decode is detected at the read
(ie. PKTAV not asserted) then the {IDLE} state is
entered. This loop of {IDLE}-{WAITPKT} will ad-
vance the FIFO up to the next valid Packet.
Any data words not delimited by PKTAV will appear
at the HIPPI channel, but the PKT and BST signals
on the HIPPI channel remain inactive. If the PKTAV
is asserted at the read, the {PENDBST} state is
entered.
{PENDBST} The PENDing BurST state is entered
when the Source Host system has a Burst of data
to send. No read operations are performed in this
state. If the “FLOF” decode is true (indicating that
the Destination is not Ready for a Burst), this state
is maintained. When the “FLOF” decode is false
then this state is exited. If the PKTAV signal is
deasserted, the {SRCERR} state is entered. If the
pending Burst has only one word either by the as-
sertion of SHBST in the first word or by the
deassertion of DATAV (the last word in the FIFO
was read), then the {LSTWD} state is entered. If the
Burst has more than one word, then the {BURST}
state is entered.
{RDIFL} The ReaD I-FieLd state is entered when a
Connect request is is initiated by the Source Host
system and there is data available from the Source
Host. When in this state the FIFO read function is
active resulting in an active low level on the NREN
output. The read operations of the FIFO will con-
tinue until the “IFLD” decode is true, at which point
the {PSTIFLD} state is entered. The decode of
“RST” or “DSCN” will exit this state back to the
{INIT}. The decode of “CON” in this state will force
entry to the {DESTERR} state.
{PSTIFLD} The PoST I-FieLd state is entered when an
I-Field is successfully read from the Source Host
system. While in this state, the I-Field data is pre-
sented to the HIPPI channel and the REQ signal is
asserted on the HIPPI channel. Although the NREN
signal remains inactive, the internal data and parity
pipeline remains active. If the I-Field was presented
from the FIFO, the FIFO output register is stable
with that data. If the FIFO data outputs were dis-
abled, any other data applied to the Source device
inputs (ie. via 3-state multiplexing) would appear at
the HIPPI channel outputs two 25MHz clock cycles
later. The decode of “DSCN” or “RST” will force
entry to {INIT}. The decode of “CON” indicates suc-
cessful connection to the HIPPI channel, and the
{IDLE} state will be entered.
{BURST} The BURST state is entered when every-
thing is prepared for transmission; a valid connec-
tion is established on the HIPPI channel, the
Source Host system has at least one Burst avail-
able, a Packet is currently active, and the Destina-
tion is capable of receiving at least one complete
Burst. In this state, Source Host system read op-
erations are performed continuously until the the
Packet is terminated, the 256th word is read, the
SHBST signal is asserted, or the Source Host FIFO
runs out of data. When any of these terminating
conditions occur, the {LSTWD} state is entered.
{LSTWD} The LaST WorD state is entered when the
last word of the current Burst has been read from
the Source Host system. No read operations are
performed in this state. This state is only one cycle
in duration, and except for error conditions, the
{LLRC} state is next.
{IDLE} The IDLE state is maintained when there is a
Connection established, but there is no Packet and
no data to transmit. No read operations are per-
formed on the FIFO in this state. When “DRDY”
indicates that Data and Burst are available, the
{WAITPKT} state is entered.
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