S19227PBI:
RUBICON
LH
DW/FEC/PM and Asynchronous Mapper
Revision 2.15 - October 2005
ADVANCE DATASHEET
1.0 Register Maps
1.1 tx_xg Register Map (1)
Addr
Reset
Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mask Registers for Events, Second Events and Delta Events in MAC Transmitter
CL_TX_XGE CL_TX_XGE CL_TX_XGE
_FRAME_UN _FRAME_OV _PKT_INS_B
DERSIZE_E_ ERSIZE_E_M UF_AVAIL_E
_MASK
ASK
MASK
CL_TX_XGE
CL_TX_XGE
_FCS_INS_E
_SCR_INH
RR
Reserved
CL_TX_XGE
CL_TX_XGE
CL_TX_XGE
_FRAME_XM
_PKT_INS_B
_FRAME_DR
IT_BAD_E_M
UF_SENT_E
OP_E_MASK
ASK
_MASK
CL_TX_XGE
CL_TX_XGE
CL_TX_XGE
CL_TX_XGE
_PAD_INSER
_PAUSE_ZE
_FCS_INH
_PAUSE_INH
T_INH
RO_INH
Reserved
F000
0xEE
F001
0x10
MAC Transmitter Inhibit Registers
F002
F003
F004
F005
F006
F007
F008
F009
F00A
F00B
0xEE
0x05
0x04
0x00
0x00
0xAA
0x00
0x00
0x00
0x00
CL_TX_XGE
_TEST_PATT
ERN_MODE
CL_TX_XGE
CL_TX_XGE
_PKT_INS_B
_PKT_INS_B
UF_PRIORIT
UF_PURGE
Y
CL_TX_XGE_SEND_RATE[7:0]
CL_TX_XGE_SEND_RATE[15:8]
CL_TX_XGE CL_TX_XGE
_PRBS31_E _PRBS31_IN
V
N
CL_TX_XGE_AUTO_PAUSE_TIME[7:0]
CL_TX_XGE_AUTO_PAUSE_TIME[15:8]
CL_TX_XGE_AUTO_PAUSE_TIME[23:16]
CL_TX_XGE_AUTO_PAUSE_TIME[31:24]
CL_TX_XGE CL_TX_XGE
_AUTO_PAU _AUTO_RES
SE
UME
CL_TX_XGE_MAC_ADDR_0[7:0]
CL_TX_XGE_MAC_ADDR_1[7:0]
CL_TX_XGE_MAC_ADDR_2[7:0]
CL_TX_XGE_MAC_ADDR_3[7:0]
CL_TX_XGE_MAC_ADDR_4[7:0]
CL_TX_XGE_MAC_ADDR_5[7:0]
CL_TX_XGE CL_TX_XGE
_IPG_REDU _AUTO_PAU
SE_EN
CE_EN
CL_TX_XGE_MAX_FRAME_SIZE[7:0]
CL_TX_XGE_MAX_FRAME_SIZE[13:8]
10GbE TX Provisioning Registers (read/write)
CL_TX_XGE_PAUSE_TIME[7:0]
CL_TX_XGE_PAUSE_TIME[15:8]
CL_TX_XGE_MIN_IPG_SIZE[7:0]
Reserved
CL_TX_XGE_ORDERED_SET[7:0]
CL_TX_XGE_ORDERED_SET[15:8]
CL_TX_XGE_ORDERED_SET[23:16]
CL_TX_XGE CL_TX_XGE
CL_TX_XGE CL_TX_XGE
CL_TX_XGE_TEST_MODE
_ORDERED_ _PKT_FLOW
_TESTDAT_ _LAN_IPG_S
[1:0]
_INH
SET_EN
ZERO_LF TRETCH_EN
F00C
0x00
F00D
F00E
F00F
F010
F011
F012
F013
F014
F015
F016
F017
F018
F019
F01A
0x00
0x00
0x00
0xC8
0x16
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
4
AMCC - Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
