Part Number - S19205CBI
Product Brief Version 1.1 - April 2001
KHATANGA
Features
• Single STS-192c/STM-64 framer/mapper device to
support 10 Gigabit Ethernet (10GbE) serial WAN,
serial LAN and STS-192c/AU-4-64c POS applica-
tions.
• Supports full duplex mapping of Ethernet frames into
a single SONET/SDH STS-192c/AU-4-64c (WIS
functionality) in compliance with IEEE P802.3ae /
D2.0 proposed baseline specification for 10GbE over
the WAN.
• SONET/SDH section/line/path processing compliant
with Telcordia GR-253, ANSI T1.105 and T1.416, and
ITU G.751, G.783 and G.804. Provides a subset of
the full SONET/SDH processing which implements
the P802.3ae / D2.0 defined 10GbE WAN Interface
Sublayer (WIS).
• Performs 10GbE MAC processing, compliant with
IEEE P802.3ae / D2.0.
• Performs 64B/66B encoding in the TX direction and
64B/66B decoding in the RX direction when operat-
ing in 10GbE mode.
• A WIS bypass mode is provided, to support 10GbE
serial LAN applications.
• Supports external MAC implementations.
• Alternatively, supports full-duplex mapping of packets
in a single SONET/SDH STS-192c/AU-4-64c per
IETF 2615 (POS).
• SONET/SDH processing includes termination and
generation of section, line, & path layers, with trans-
port/section and path overhead interfaces in both
transmit and receive directions.
ADVANCED PRODUCT BRIEF
10 Gigabit Ethernet MAC and PHY / OC-192c POS Framer and Mapper
General Description
• POS processing includes HDLC framing, payload
scrambling (x
43
+ 1) and transparency processing.
• 10GbE MAC transmit processing includes frame
assembly, pad insertion, and CRC generation.
• 10GbE MAC receive processing includes Ethernet
framing, CRC checking, and frame size monitoring.
• Supports 802.3x PAUSE flow control.
• Provides counters to support implementation of
RMON, 802.3 MIBs.
• Provides a 622.08 MHz 16-bit bus interface on the
line side in both the TX and RX directions (SFI-4/
XSBI compliant).
• Provides a 644 MHz 16-bit LVDS interface on the line
side in both TX and RX directions for LAN PHY appli-
cations (XSBI).
• Provides a 64-bit, 200 MHz FlexBus-4
TM
system
interface (SPI-4 Phase 1 compliant).
• Direct Map Mode for mapping of any traffic type in
SONET/SDH STS-192c/AU-4-64c payloads
• 16-bit synchronous microprocessor interface for con-
figuration, control, and status monitoring.
• Provides a 622.08 MHz 16-bit line bus to support
Automatic Protection Switching (APS) configurations.
• Packaged in a 624-pin CBGA.
• Implemented in .18 micron CMOS, 1.8V and 2.5V
technology.
S19205CBI Block Diagram
PROT_DATA_OUT[15:0]
TX_TOH_FRM_OUT
TX_TOH_CLK_OUT
PROT_CLK _OUT
TX_TOH_DATA_IN
RDYB(DTACKB)
BUSMODE
APS_INTB
UPCLK
LINE SIDE INTERFACE
MUX
SEL
TOH INSERT
RSTB
INTB
D[15:0]
ADDR[12:0]
CSN
WRB(RWB)
GPIO[15:0]
MICROPROCESSOR I/F
SPE
GEN
POH
MON
64B66B
Encoder
Encoder
10G
MAC
HDLC
Proc
HDLC
Proc
64B66B
Decoder
SEL
JTAG
TDO
TCK
TMS
TDI
TRSTB
TS_EN
10G
MAC
SYSTEM
INTRFC
FIFO
Control
STX_DATA_IN[63:0]
FRGEN
FRTX
TOH
MON.
MUX
SEL
RX_DATA_IN[15:0]
RX_CLK_IN
LOC
DET
SEL
LBK
SEL
FRMR
FRAM
SEL
TX_CLK_OUT
TX_DATA_OUT[15:0]
PTR
INT
SYSTEM
INTRFC
FIFO
SRX_DATA_OUT[63:0]
Control
TOH EXTRACT
RX_ALM_OUT
RX_LOSEXT
RX_REFCLK_IN
RX_TOH_DATA_OUT
RX_TOH_FRM_OUT
RX_TOH_CLK_OUT
FRM
PROT_DATA_IN[15:0]
SYS_REFCLK_IN
SYS_ASYNC_FRM_IN
SYS_REFCLK_OUT
PROT_CLK_IN
AMCC - Confidential and Proprietary
Advanced Information
- The information contained in this
document is about a product in its design stage and is subject
to change without notice at any time. All features described
herein are design goals. Contact AMCC for updates to this
document and the latest product status.
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
