QT2022/32 - Data Sheet: DS3051
8 Control and Status Pins Detailed Description
8.1 General Notes
8.1.1 IO Polarity
The user can control the polarity of most low speed CMOS pins (MDIO registers 1.D003h, 1.D005h). Changing the
polarity of a pin inverts the logic of the pin function.
8.1.2 IO Monitoring Via MDIO
For debugging purposes, the user can read MDIO register 1.D002h to see the state of most low speed CMOS
inputs (value after PAD and after inversion if enabled). Exceptions are PRTAD<4:0>, LANMODE, RESETN. The
state of most low speed CMOS outputs (value before PAD and before inversion if enabled) can be found in MDIO
register 1.D004h.The state of the 3 LED pins can be checked in the LED Configuration Registers. See Section 8.6
on page 70 for details.
8.2 Control (Input) Pins (QT2022 and QT2032)
The pins described in this section are common to both the QT2022 and QT2032. All pins have the same function
for both products.
The low speed control input pins are listed in Table 3, “QT2022/32 Ball Assignment & Signal Description,” on
page 13. The inputs have switching points which are compatible with 1.2V CMOS logic, but can tolerate up to 3.3V
logic levels.
8.2.1 Laser Fault Control Pin (TXFAULT)
The TXFAULT fault input is used to indicate that there is a problem with the external laser or laser driver. TXFAULT
does not have any effect on TXENABLE.
8.2.2 XFP Mode Control Pin (XFP)
The XFP input pin is used to configure the chip to support system cards interfacing with an XFP module (XFP
mode). Several features of the chip are changed or disabled when the XFP pin is high. When the XFP pin is low,
the chip follows the default behavior. The default logic should be used for XENPAK / XPAK / X2 module applica-
tions. There is an internal pulldown within the XFP input, so this is the default state if left unconnected.
The following features are changed or disabled when in XFP mode:
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TXPLLOUT default frequency changed to baudrate / 64 (161.13 MHz); output turned on by default
RXLOSB_I input pin reassigned as RX_LOS input for XFP module; logic polarity is inverted
TXON input pin redefined as an output to drive MOD_DESEL of XFP module
EEPROM_PROT input pin reassigned to input Mod_ABS from XFP module
TXFAULT input pin reassigned as Mod_NR from XFP module
LASI_INTB input pin reassigned as interrupt from XFP module
TXENABLE output pin reassigned to drive TX_DIS input of XFP module; logic polarity is inverted
LOSOUTB output pin reassigned to drive P_DOWN/RST input of XFP module
TRST_N pin no longer used as connection point for external powerup reset cap.
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