QT2022/32 - Data Sheet: DS3051
11.7 Disabling the Idle Decode Process
The XGXS block of the chip converts the incoming XAUI signal from a 10 bit-encoded signal to an 8-bit encoded
signal. The chip also decodes all the K28.0, K28.3 and K28.5 idle codes to the same 8-bit code, /I/ = 0x07, as spec-
ified in IEEE 802.3-2005 Table 48-3. These idle codes will typically be transmitted to a far-end SerDes (such as
another QT2022/32). The far-end SerDes will convert the 8-bit idle codes into 10-bit encoded K28.0, K28.3 and
K28.5 codes, following the rules specified by the idle randomization process (as per IEEE 802.3-2005 Clause
48.2.4.2). The original idle code order will not be preserved.
The XGXS idle decode process can be disabled by setting MDIO register bit 4.C007h.8 = 1. In this test mode, the
K28.0, K28.3 and K28.5 codes are decoded to their native 8-bit code as given in IEEE 802.3-2005 Table 49-1
(K28.0 -> 0x1C, K28.3 -> 0x7C, K28.5 -> 0xBC). There will be no idle codes, 0x07, generated in the signal.
When this modified signal is passed through the receive path of the QT2022/32, the idle codes will pass through
the chip unmodified. The idle randomization process will not operate on them. The 8b/10b encoder will convert
them to their original 10-bit code words, thereby preserving the original order of the signal.
This feature is useful when testing the XAUI interface using an external pattern generator & error detector that is
not protocol-aware and cannot handle the idle randomization normally. Note that the receive 8b/10b encoder pro-
cess will choose one of two running disparities, depending on the signal. If the disparity does not match that
expected by the external error detector, errors will be reported. Therefore, it is important to check for both possible
disparities. For more information on disparity, consult IEEE-802.3-2002 Clause 36.2.4.4; also review Clause
36.2.4.7.1 for 8b/10b valid code-groups. For information on disparity as it relates to CJPAT, consult IEEE 802.3-
2005 Clause 48A.5.1.
When the idle decode process is disabled, the rate compensation capability of the chip will fail to function properly.
It fails because the rate compensation block operates on standard 8-bit idle codes, 0x07, which are absent from
the signal. Therefore, this feature should not be used during normal operation. To use this feature properly, supply
a reference clock to the chip that is synchronous to the incoming signal. If an asynchronous reference clock is sup-
plied and the chip must perform a rate compensation, error codes will be generated.
This feature does not work on the QT2032 when operating in WAN mode.
11.8 Test Access Port and Boundary Scan
The QT2022/32 has a test-access port (TAP) and a boundary scan (BSCAN) chain compliant with IEEE standards
1149.1 and 1149.6 (JTAG).
11.8.1 BSCAN chain
The following pins are on the BSCAN chain:
•
•
AC pins: all XAUI I/O
DC pins: all low-speed digital I/O
The following pins are not in the BSCAN chain:
•
•
all supplies and grounds
all analog pins for external component connections (RXFP/N/C, TXFP/N/C, RXICXP/N, ITH_LOS, XBIAS,
RxXLEVEL, TXLEVEL, RXIPUMP, TXIPUMP, PHASE_OFFSET)
•
•
all lab test I/O (TxXMONCVP/N, RXPLLOUTP/N, TXPLLOUTP/N)
all 10G I/O (RXINP/N, TXOUTP/N)
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