QT2022/32 - Data Sheet: DS3051
11. Activate both generators. Set them to Burst Mode and Fixed Data Type. Do this by writing 16’h0103 to register
3.C020h.
12. Wait sufficiently long to receive all packets within one burst. Calculate the required delay based on packet
length, IPG and packet count.
13. Read the RX and TX error counters (reg 3.C034h and 3.C036h). They will read all zeroes.
14. Read the RX and TX pkt counters (reg 3.C035h and reg 3.C037h). They should show the same value as reg
3.C024h.
To send a second burst:
1. Set the TX and RX generators to Idle Mode. Do this by writing 16’h0003 to reg 3.C020h.
2. Read all error/status registers to clear them. They are registers 3.C034h, 3.C035h, 3.C036h and 3.C037h.
3. Repeat steps 11 through 14.
11.6.5 Purposely creating errors
1. Connect the TX XAUI lanes to the RX XAUI lanes.
2. Connect the TX FIBER to the RX FIBER.
3. Write a random value to registers 3.C031h and 3.C032h. The 32 incoming XGMII data bits will be compared to
those registers.
4. Write 4’h0 to register 3.C033h.3:0, since we will be comparing on data octets (as opposed to reserved control
codes).
5. Activate both packet checkers and program them to expect fixed data. Do this by writing 16’h0003 to register
3.C030h.
6. Read all error/status registers to clear. They are registers 3.C034h, 3.C035h, 3.C036h and 3.C037h.
7. Write in registers 3.C021h and 3.C022h values that are different from the values in registers 3.C031h and
3.C032h.
8. Write 4’h0 to reg 3.C023h.3:0.
9. Set the burst size to a non-zero value by writing to the register 3.C024h. If the burst size is set to zero, no
packets will be sent by the generator (only idles).
10. Set the packet size to a non-zero value by writing to the register 3.C025h.
11. Set the IPG size to a non-zero value by writing to the register 3.C026h. Although it is legal to write zero to that
register, the result would be back-to-back packets without any IPG.
12. Activate both generators. Set them to Burst Mode and Fixed Data Type. Do this by writing 16’h0103 to register
3.C020h.
13. Wait sufficiently long to receive all packets within one burst. Calculate the required delay based on packet
length, IPG and packet count.
14. Read the RX and TX error counters (reg 3.C034h and 3.C036h). They will read non-zero values.
15. Read the RX and TX pkt counters (reg 3.C035h and reg 3.C037h). They should show the same value as reg
3.C024h.
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