QT2022/32 - Data Sheet: DS3051
11.6.2 Packet Generator Characteristics
•
The generator can output complete packets with either fixed or incremental data. This is called the packet
type feature and is controlled via register 3.C020h.5:4.
•
When fixed data is chosen, the contents of registers 3.C021h and 3.C022h are transmitted inside the
packet. These register value contents are repeated for the length of the packet. It can also output the con-
tents of registers 3.C021h and 3.C022h without adding //S// or //T// columns. This can be useful to send cer-
tain reserved control codes, for example.
•
•
•
When incremental data is chosen, the data byte values begin at 00 and bitwise increment to stuff the data
field in a rollover fashion. The data is filled at the 8-bit level.
The generator can output data continuously (Continuous Mode) or in bursts (Burst Mode). The generator
can also be put in Idle Mode. In this case, only XGMII idles will be output by the generator.
Once all the packets in a burst are sent, the generator will send only idles. To re-send another burst, the
generator must be taken out of Burst Mode and into Idle Mode. When it is put back into Burst Mode, another
burst of packets will be sent.
•
•
Packet length is controlled by register 3.C025h and the IPG is controlled by register 3.C026h.
Note: Asserting reset will not resend another burst. Doing so would clear all the generator control registers
to their default values.
11.6.3 Packet Checker Characteristics
•
The checker can expect complete packets with either fixed or incremental data. This is called the packet
type feature. It is controlled via register 3.C030h.[5:4].
•
When fixed data is chosen, the contents of registers 3.C031h and 3.C032h are expected inside the packet.
It can also expect the contents of registers 3.C031h and 3.C032h without //S// or //T// columns. This can be
quite useful when testing certain reserved control codes, for example.
•
•
When incremental data is chosen, the expected data byte values begin at 00 and bitwise increment within
the data field in a rollover fashion. The data is interpreted at the 8-bit level.
Expected packet length and IPG is not programmed for the checkers.
11.6.4 Example Uses
Basic use, both generators on with Burst Mode and both checkers on
1. Connect the TX XAUI lanes to the RX XAUI lanes.
2. Connect the TX FIBER to the RX FIBER.
3. Write a random value to registers 3.C031h and 3.C032h. The 32 incoming XGMII data bits will be compared to
those registers.
4. Write 4’h0 to register 3.C033h.[3:0], since we will be comparing on data octets (as opposed to reserved con-
trol codes).
5. Activate both packet checkers and program them to expect fixed data. Do this by writing 16’h0003 to register
3.C030h.
6. Read all error/status registers to clear. They are registers 3.C034h, 3.C035h, 3.C036h and 3.C037h.
7. Write the same values contained in registers 3.C031h and 3.C032h in registers 3.C021h and 3.C022h.
8. Set the burst size to a non-zero value by writing to the register 3.C024h. If the burst size is set to zero, no
packets will be sent by the generator (only idles).
9. Set the packet size to a non-zero value by writing to the register 3.C025h.
10. Set the IPG size to a non-zero value by writing to the register 3.C026h. Although it is allowed to write zero to
that register, the result would be back-to-back packets without any IPG.
104
AppliedMicro - Confidential & Proprietary
Revision 5.11
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
