Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Table 2. DCR Address Map
Function
Base Address
Start Address
End Address
Size
1
1
Total DCR Address Space
000
3FF
1KW (4KB)
By function:
Reserved
000
00C
00E
010
012
014
020
030
040
050
060
080
090
0A0
0B0
0C0
0D0
0E0
0F0
100
120
140
160
168
180
200
240
00B
00D
00F
011
013
01F
02F
03F
04F
05F
07F
08F
09F
0AF
0BF
0CF
0DF
0EF
0FF
11F
13F
15F
167
17F
1FF
23F
3FF
12W
2W
Clocking Power On Reset (CPR)
System DCRs (SDR)
Memory Controller
External Bus Controller (EBC)
Reserved
00 0000 110x
00 0000 111x
00 0001 000x
00 0001 001x
2W
2W
2W
12W
16W
16W
16W
16W
32W
16W
16W
16W
16W
16W
16W
16W
16W
32W
32W
32W
8W
L2 Cache as SRAM
L2 Controller
00 0010 xxxx
00 0011 xxxx
00 010x xxxx
Memory Queue
Reserved
I2O/DMA Controller
PLB Arbiter
00 011x xxxx
00 1000 xxxx
00 1001 xxxx
00 1010 xxxx
00 1011 xxxx
00 1100 xxxx
00 1101 xxxx
00 1110 xxxx
00 1111 xxxx
01 000x xxxx
01 001x xxxx
PLB-to-OPB Bridge
PLB-to-AHB Bridge
On-Chip Memory (OCM)
Universal Interrupt Controller 0
Universal Interrupt Controller 1
Universal Interrupt Controller 2
Universal Interrupt Controller 3
PCI Express 0
PCI Express 1
Reserved
Power Management
Reserved
01 011x xxxx
24W
128W
64W
448W
Ethernet MAL
01 1xxx xxxx
10 00xx xxxx
DMA Controller
Reserved
Notes:
1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One
kiloword (1024W) equals 4KB (4096 B).
10
AMCC Proprietary
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