Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 25)
Signal Name
Ball
U12
U15
U17
U20
U26
V09
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
V12
GND
V15
GND
V18
GND
Y04
GND
Y10
GND
Y17
Power
56
GND
Y23
GND
AC01
AC07
AC13
AC14
AC20
AC26
AF04
AF10
AF17
AF23
L01
GND
GND
GND
GND
GND
GND
GND
GND
GND
[GPIO00] [TRCCLK] High Z
[GPIO01] [TRCBS0] High Z
[GPIO02] [TRCBS1] High Z
[GPIO03] [TRCBS2] High Z
[GPIO04] [TRCES0] High Z
[GPIO05] [TRCES1] High Z
[GPIO06] [TRCES2] High Z
[GPIO07] [TRCES3] High Z
[GPIO08] [TECES4] High Z
[GPIO09] [TRCTS0] High Z
[GPIO10] [TRCTS1] High Z
H01
F01
L02
GPIO Peripherals
K03
G02
M05
F02
55
Note: Trace can be enabled at reset by setting
SDR0_SDSTP1[DBG] (bit 27) to 1 in the serial
bootstrap ROM.
J03
H04
J05
22
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
