Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Ethernet Controller Interface
Preliminary Data Sheet
The Ethernet support interfaces to the physical layer, but the PHY is not included on the chip.
Features include:
• One 10/100/1000 interface running in full- and half-duplex modes
– One full Media Independent Interface (MII) with 4-bit parallel data transfer
– One Gigabit Media Independent Interface (GMII)
I2O/DMA Controller
The I20/DMA controller provides support for I20 messaging and two DMA controllers (DMA0 and DMA1). I2O
manages Message Frame Address (MFA) FIFOs or queues in memory in response to I2O register reads and
writes and transfers message frames. The DMAs provide normal memory access support to ease the CPU burden.
I2O features include:
• I2O pull- and push-messaging methods
• Dynamic message frame size
• Programmable FIFO size (4096 64-bit MFAs maximum)
• 64-bit and 32-bit MFA sizes
• Three interrupt gathering methods
• Registered MFA prefetch and posting
• 32-bit inbound and outbound doorbell registers
• Four 32-bit scratch pad registers
DMA features include:
• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)
• 512-byte buffering
• Simultaneous fill and drain (PLB read/write pipelining)
• Any source PLB address to any destination address
• No memory alignment restrictions on source or destination
• 32-byte command descriptor block
• Maximum transfer size of 16MB
• 64-bit addressing
• 1KB buffering (DMA1 only)
• Prefetch indicators for PCI-X buffer management (DMA1 only)
Optional RAID 5 and RAID 6 Acceleration Hardware
The 440SPe provides integrated acceleration hardware that implements high throughput RAID 5 and RAID 6
algorithms to compute the single parity P for RAID 5, and dual parity P & Q for RAID 6. RAID 5 is used to recover
data in the case of a single disk drive failure, and RAID 6 provides for data recovery if two disk drives fail.
The 440SPe offers a choice of two XOR engines for computing the P parity. The first choice is available with the
XOR/DMA2 acceleration unit and is used for RAID 5. The second choice for XOR parity computation, along with
8
the RAID 6 Galois Field GF(2 )-based polynomial computations, resides inside the Memory Queue functional block
of the Memory Controller unit. The Galois Field polynomial used with the 440SPe is programmable and can be one
of sixteen available irreducible polynomials, including 14d and 11d.
The RAID 5 and RAID 6 parity computations performed in the Memory Queue are assisted by the two-channel
DMA engine of the I2O/DMA controller unit, designated as DMA0 and DMA1. The RAID acceleration hardware
also provides various alternatives for balancing load and performance, depending on customer-specific application
firmware. The two-way crossbar bus architecture can perform data read and write operations simultaneously,
resulting in extremely high throughput.
RAID 6 capability is available only with the RAID-enabled part numbers (PPC440SPe-RpBfffC) as indicated in the
ordering information section of this data sheet.
AMCC Proprietary
13
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
