Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Table 27. I/O Timing—DDR SDRAM T and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 166MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (6ns x 0.25 = 1.5 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, TSD − 1.5 + 0.25TCYC).
TSD (ns)
THD (ns)
Signal Names
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
Reference Signal
DQS0
1.37
1.41
1.40
1.41
1.45
1.40
1.46
1.45
1.46
1.23
1.18
1.17
1.20
1.18
1.18
1.17
1.10
1.18
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DDR SDRAM Read Operation
The read data capture logic is responsible for capturing the data outputs from the SDRAM devices and passing the
data back to the system clock domain. The data strobe signal (DQS) signals used to capture data are delayed to
ensure that the rising and falling edges of these strobes are in the middle of the valid window of data.
DDR devices send a DQS coincident with the read data so that the data can be reliably captured by the
PPC440GRx. The edges of these strobe signals are aligned with the data output by the SDRAM devices.
In order to reliably latch the data into a synchronizing FIFO, the PPC440GRx produces an internal, delayed version
of DQS. The amount of delay is user programmable. In the example shown in Figure 12, DDR SDRAM DQS Read
Timing, the delay is set to approximately 25% of the system clock. A delay compensation circuit in the PPC440GRx
keeps this delay constant.
Figure 12. DDR SDRAM DQS Read Timing
MemClkOut
DQS
MemData
Delayed DQS
(data strobe)
DQS delay
AMCC Proprietary
85
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
