Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Thermal Monitor
Thermal monitoring of the chip is accomplished using the PNP transistor (β ≈ 2) provided on the chip. The collector
of the transistor is connected to ground (GND). The emitter (TherMonA) and base (TherMonB) are connected to
chip pins. A voltage measurement (V
and V
) across the TherMonA and TherMonB pins at the two current
BE1
BE2
values I and I provides the chip temperature in °K according to the equation:
1
2
-19
-23
T = (q/nk)(V
−V
)/ln(I /I ) °K where q = 1.602 176 53×10 , n = 1.0 ± 0.015, and k = 1.380 6505×10
.
BE2
BE1
2 1
Note: V
and V
should be specified in Volts. I and I can be any units of measure provided they are the
1 2
BE2
BE1
same. The small values require precision measurement and current sources.
The calculated on chip (ball to ball) series resistance for the PPC440EPx thermal monitor circuit is 2.0 ohms. The
thermal sensor reflects the PPC440EPx junction temperature.
PPC440EPx
C
E
TherMonA
TherMonB
I , I (Max = 300μA)
1
2
V
, V
BE1 BE2
B
Note: The bias voltage VEB should be between +0.5V and +0.7V.
Test Conditions
Output
Pin
Clock timing and switching characteristics are specified in accordance with operating
conditions shown in Table 10 on page 66. AC specifications are characterized with
50pF
V
= +1.5V, T = +85 °C and a 50pF test load as shown in the figure to the right.
DD
C
Table 18. Clocking Specifications
Symbol
SysClk Input
FC
Parameter
Min
Max
Units
Notes
Frequency
33.33
15
66.66
30
MHz
ns
TC
Period
Edge stability (cycle-to-
cycle jitter)
TCS
–
±0.15
ns
ns
ns
40% of nominal
period
60% of nominal
period
TCH
High time
Low time
40% of nominal
period
60% of nominal
period
TCL
Note: Input slew rate ≥ 1V/ns
PLL VCO
FC
TC
Frequency
Period
600
1333.33
1.66
MHz
ns
0.750
Processor (CPU) Clock
FC
Frequency
333.33
666.66
MHz
1
AMCC Proprietary
73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
