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PPC440EPX-SPAFFFTS 参数 Datasheet PDF下载

PPC440EPX-SPAFFFTS图片预览
型号: PPC440EPX-SPAFFFTS
PDF下载: 下载PDF文件 查看货源
内容描述: 440EPx的PowerPC嵌入式处理器 [PowerPC 440EPx Embedded Processor]
分类和应用: PC
文件页数/大小: 94 页 / 3193 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.26 – October 15, 2007  
440EPx – PPC440EPx Embedded Processor  
Preliminary Data Sheet  
Table 25. I/O Timing—DDR SDRAM T , T , and T  
SK SA  
HA  
Notes:  
1. Clock speed is 166MHz. TSK is referenced to MemClkOut falling edge. TSA and THA are referenced to MemClkOut rising  
edge.  
2. The timing in this table assumes a single registered DIMM load on the outputs. To adjust the timing for unbuffered DIMMs,  
use the following values by subtracting them from T and adding them to T and T :  
SA  
SK  
HA  
5 loads adjust by 0.41ns  
9 loads adjust by 1.12ns  
18 loads adjust by 2.12ns  
3. To obtain adjusted TSA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and subtract  
TSK maximum (0.5TCYC TSKmax).  
4. To obtain adjusted THA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add  
TSK minimum (0.5TCYC + TSKmin).  
TSK (ns)  
TSA (ns)  
THA (ns)  
Signal Name  
Minimum  
Maximum  
Minimum  
Minimum  
MemAddr00:13  
BA0:2  
BankSel0:1  
ClkEn  
-0.960  
-0.270  
3.27  
2.04  
CAS  
RAS  
WE  
Table 26. I/O Timing—DDR SDRAM T and T  
SD  
HD  
Notes:  
1. TSD and THD are measured under worst case conditions.  
2. Clock speed for the values in the table is 166MHz.  
3. The time values in the table include 1/4 of a cycle at 166MHz (6ns x 0.25 = 1.5 ns).  
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4  
of the cycle time for the lower clock frequency (for example, TSD 1.5 + 0.25TCYC).  
TSD (ns)  
THD (ns)  
Signal Names  
MemData00:07, DM0  
MemData08:15, DM1  
MemData16:23, DM2  
MemData24:31, DM3  
MemData32:39, DM4  
MemData40:47, DM5  
MemData48:55, DM6  
MemData56:63, DM7  
ECC0:7, DM8  
Reference Signal  
DQS0  
1.37  
1.41  
1.40  
1.41  
1.45  
1.40  
1.46  
1.45  
1.46  
1.23  
1.18  
1.17  
1.20  
1.18  
1.18  
1.17  
1.10  
1.18  
DQS1  
DQS2  
DQS3  
DQS4  
DQS5  
DQS6  
DQS7  
DQS8  
DDR SDRAM Read Operation  
The read data capture logic is responsible for capturing the data outputs from the SDRAM devices and passing the  
data back to the system clock domain. The data strobe signal (DQS) signals used to capture data are delayed to  
ensure that the rising and falling edges of these strobes are in the middle of the valid window of data.  
DDR devices send a DQS coincident with the read data so that the data can be reliably captured by the  
PPC440EPx. The edges of these strobe signals are aligned with the data output by the SDRAM devices.  
In order to reliably latch the data into a synchronizing FIFO, the PPC440EPx produces an internal, delayed version  
of DQS. The amount of delay is user programmable. In the example shown in Figure 12, the delay is set to  
approximately 25% of the system clock. A delay compensation circuit in the PPC440EPx keeps this delay  
AMCC Proprietary  
89  
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