Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Block Diagram
Figure 2. PPC440EPx Functional Block Diagram
10
Clock
Control,
Reset
External
Power
Mgmt
Interrupts
66MHz max
- 32 bits
- 6 devices
83MHz max
- 30-bit addr
- 32/16-bit data
DCRs
Timers
MMU
UIC
PPC440
DCR Bus
Processor
FPU
External
Peripheral
Controller
NAND
PCI
Trace
JTAG
Flash
Bridge
Controller
32KB
32KB
D-Cache
I-Cache
Security
(optional)
SRAM
16KB
PLB-PLB
Bridges
PLB (PLB4—128 bits)
PLB (PLB3—64 bits)
DMA
DMA
Controller
OPB OPB OPB
Bridge
Bridge
OPB
Bridge
GPT
BSC
Controller
Bridge
DDR2/1
SDRAM
Controller
On-chip Peripheral Bus (OPB 0)
OPB 2
OPB 1
Device
USB 2.0
Ethernet
10/100/1000
x2
Host
IIC
UART
x4
SPI
GPIO
333MHz max
x2
MAL
data rate
- 14-bit addr
- 64/32-bit data
RGMII
ZMII
2.0 PHY
D+/D−
™
The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect Bus Architecture.
Address Maps
The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map.
This address map defines the possible contents of various address regions which the processor can access. The
second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440EPx processor through the use of mtdcr and mfdcr instructions.
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
