Revision 1.26 - June 16, 2008
PowerPC 440SPe Embedded Processor
Data Sheet
Table 20. DDR SDRAM I/O Read Timing—T and T
SD
HD
Notes:
1. T
and T
are measured under worst case conditions.
SD
HD
2. Clock speed for the values in the table is 333.33MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (3ns x 0.25 = 0.75 ns).
4. To obtain adjusted T and T values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4
SD
HD
of the cycle time for the lower clock frequency (e.g., T
- 0.75 + 0.25T
).
SD
CYC
Read Data vs DQS Set up
(ns)
Read Data vs DQS Hold
(ns)
Signal Names
MemData00:07
Reference Signal
T
T
SD
0.00
HD
1.00
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
Figure 10. DDR SDRAM Memory Data and DQS
DQS
T
SD
MemData
T
HD
AMCC Proprietary
75
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
