Revision 1.26 - June 16, 2008
PowerPC 440SPe Embedded Processor
Data Sheet
Table 12. Clocking Specifications
Symbol
Parameter
Min
Max
Units
Processor Clock (CPU Clock)
FC
TC
Frequency
Period
400
1.5
800*
2.5
MHz
ns
MemClkOut
FC
Frequency
Period
200
333.33
MHz
ns
TC
3
5
TCH
High time
45% of nominal period
55% of nominal period
ns
OPB Clock and PerClk
FC
TC
Frequency
Period
–
83.33
–
MHz
ns
12
MAL Clock
FC
Frequency
Period
45
12
83.33
22.2
MHz
ns
TC
Figure 4. Clock Timing Waveform
T
T
CL
CH
T
C
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440SPe. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC440SPe the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC440SPe with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation cannot exceed -1%, and the modulation frequency cannot exceed 40kHz.
In some cases, on-board PPC440SPe peripherals impose more stringent requirements.
• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
modulation.
• Use the DDR SDRAM MemClkOut since it also tracks the modulation.
AMCC Proprietary
63
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
