Revision 1.26 - June 16, 2008
PowerPC 440SPe Embedded Processor
Data Sheet
I/O Specifications
Table 13. Peripheral Interface Clock Timings
Parameter
PCIX0Clk input frequency (asynchronous mode)
PCIX0Clk period (asynchronous mode)
PCIX0Clk input high time
PCIX0Clk input low time
Min
Max
Units
MHz
ns
Notes
–
133.33
2
7.5
–
40% of nominal period
60% of nominal period
ns
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency
EMCTxClk period
160
–
ns
160
–
ns
2.5
25
MHz
ns
40
400
EMCTxClk input high time
EMCTxClk input low time
EMCRxClk input frequency
EMCRxClk period
35% of nominal period
–
ns
35% of nominal period
–
ns
2.5
25
MHz
ns
40
400
EMCRxClk input high time
EMCRxClk input low time
PerClk output frequency (for sync. slaves)
PerClk period
35% of nominal period
35% of nominal period
–
–
ns
–
ns
83.33
–
MHz
ns
12
PerClk output high time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
ns
PerClk output low time
ns
1000/(2T
1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
1
1
1
OPB
2T
T
+2
–
–
OPB
+1
UARTSerClk input high time
UARTSerClk input low time
ns
OPB
T
+1
–
ns
OPB
TmrClk input frequency
TmrClk period
–
100
–
MHz
ns
10
TmrClk input high time
TmrClk input low time
Notes:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. T
OPB
is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of
the PLB clock. The maximum OPB clock frequency is 83.33 MHz. Refer to the Clocking chapter of the PPC440SPe
Embedded Processor User’s Manual for details.
2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz.
AMCC Proprietary
65
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
