Revision 1.26 - June 16, 2008
PowerPC 440SPe Embedded Processor
Data Sheet
• Buffering in each PCI Express Port for the following transaction types:
– 4K byte Replay buffer: up to 8 in flight transactions
– 2K bytes for Outbound posted Writes
– 8K bytes for Outbound Reads completion
• 2K prefetch request from first I2O/DMA PLB Master
• 1K prefetch request from 2nd I2O/DMA PLB Master
• 1K prefetch request from first PCIE 4x links
• 1K prefetch request from 2nd PCIE 4x links
• 256 byte from the PPC440
– 2K bytes for Inbound posted Writes
– 2K bytes for Inbound Reads completion
• Parity checking on each buffer
• POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs
• PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM
• INTx Interrupts support (PCI legacy):
– up to 4 INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types Generation for Endpoints
• MSI - Message Signaled Interrupts
– MSI Generation for End Point
– MSI Termination for Root Ports
– MSI_X Termination for Root Ports
DDR PCI-X Interface
The DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local
memory. The PCI-X interface supports 64-bit PCI-X bus in DDR mode 2. It can be configured for either host or
adapter mode. PCI 32/64-bit legacy mode, compatible with PCI Version 2.3, is also supported.
Features include:
• PCI-X 2.0
– Split transactions
– Frequency to 266MHz
– 32- and 64-bit address/data bus
– ECC supported for 266MHz Mode 2 only
• PCI 2.3 backward compatibility
– Frequency to 66MHz
– 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device PCI interface
• Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can
be disabled for use with an external arbiter
• Support for PLB-based (external to PLB–PCI-X bridge) I2O
• Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management Version 1.1
• PCI arbitration function with PCI-X Mode 2 support (optional)
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI-X bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (Type 0 and Type 1)
– Single beat special cycles
AMCC Proprietary
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
