Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
PPC440SP Functional Block Diagram
Figure 2. PPC440SP Functional Block Diagram
Clock,
Power
Control,
Reset
Mgmt
Universal
Interrupt
Controller
MMU
Timers
UART2
DCRs
UART1
UART0
IIC1
IIC0
PPC440
Processor Core
GPIO
GPT
DCR Bus
Trace
JTAG
On-chip Peripheral Bus (OPB)
32KB
32KB
D-Cache
I-Cache
OPB
Bridge
L2 Cache/SRAM
PLB
Arbiter
Processor Local Bus (PLB)
Ethernet
External
Bus Controller
(EBC)
Low Latency (LL) Segment
High Bandwidth (HB) Segment
10/100/
1000
MAL
(EMAC)
MII,
GMII
DDR PCI-X
Memory
Queue
XOR/DMA
Accelerator
Unit
I2O/DMA
Controller
(DMA0 and
DMA1)
PCI2
Local
PCI0 PCI1
Host Local
64 bits 64 bits
DDR2 SDRAM
Controller
(DMA2)
32 bits
®
The PPC440SP is a System on a chip, which uses IBM CoreConnect Bus™ Architecture.
Implemented with the Crossbar option, the IBM CoreConnect buses provide:
• 128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data
paths (10.6GB/sec total)
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various processor accessible address regions. The second address
map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the
PPC440SP processor through the use of mtdcr and mfdcr instructions.
AMCC Proprietary
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
