Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 20. DDR SDRAM I/O Read Timing—T and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 333.33MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (3ns x 0.25 = 0.75 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (e.g., TSD - 0.75 + 0.25TCYC).
Read Data vs DQS Setup
TSD (ns)
Read Data vs DQS Hold
THD (ns)
Signal Names
MemData00:07
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
Figure 10 shows the data strobe (DQS) and the data to be coincident. There is actually a slight skew as specified
by the SDRAM specifications, and there can be additional skew due to loading and signal routing. It is
recommended that the signal length for all of the eight DQS signals be matched.
Figure 10. DDR SDRAM Memory Data and DQS
DQS
TSD
MemData
THD
AMCC Proprietary
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
