Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
Signal Functional Description (Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
System Interface
Description
I/O
Type
Notes
SysClk
SysErr
Main system clock input.
Clock
O
3.3V LVTTL
3.3V LVTTL
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. The signal is implemented
as an open-drain output (two states; 0 or open circuit).
SysReset
I/O
3.3V LVTTL
1, 2
During chip power-up, this signal must be low from the start of VDD
ramp-up until at least 16 SysClk cycles after VDD is stable.
TmrClk
Halt
Processor timer external input clock.
Halt from external debugger.
I
I
3.3V LVTTL
3.3V LVTTL
1, 4
General purpose I/O 0 through 10. To access these functions,
software must set DCR register bits.
GPIO00:31
I/O
3.3V LVTTL
3.3V tolerant
2.5V CMOS
TestEn
RcvrInh
RefVEn
Test Enable.
I
I
I
3
Receiver Inhibit. Active only when TestEn is active.
3.3V LVTTL
Reference Voltage Enable. Do not connect for normal operation.
Pull up for Boundary Scan Description Language (BSDL) testing.
3.3V LVTTL
w/pull-down
Driver Inhibit. Used for test purposes only. Tie up for normal
operation
3.3V LVTTL
w/pull-up
DrvrInh2
I
2
56
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
