Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
I/O Specifications—All Speeds (Sheet 2 of 7)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Ethernet MII Interface
EMCRxD0:3
4
4
1
1
na
na
na
na
5.1
5.1
6.8
6.8
EMCRxClk
EMCRxClk
1
1
EMCRxDV
1,
async
EMCRxClk
na
na
na
na
5.1
6.8
EMCRxErr
EMCTxD0:3
EMCTxEn
4
1
na
15
15
na
2
5.1
5.1
5.1
6.8
6.8
6.8
EMCRxClk
EMCTxClk
EMCTxClk
1
1
1
na
na
na
na
2
1,
async
EMCTxClk
EMCTxErr
EMCCrS
na
na
na
na
na
15
na
na
2
na
5.1
5.1
na
6.8
6.8
EMCTxClk
EMCMDClk
1
1,
async
na
1,
async
EMCCD
na
na
na
na
5.1
5.1
5.1
6.8
6.8
6.8
EMCMDIO
EMCMDClk
1
1,
async
na
na
Ethernet RMII Interface
EMC0RxD0:1
EMC0RxErr
2
2
1
1
na
na
na
11
11
na
na
na
11
na
na
na
2
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMC0CrSDV
EMC0TxD0:1
EMC0:1TxEn
EMC1RxD0:1
EMC1RxErr
na
na
na
na
2
na
na
na
2
EMC1CrSDV
EMC1TxD0:1
na
na
na
na
3,
async
EMCRefClk
na
na
na
na
AMCC
71
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
