Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
• OPB
- Dynamic bus sizing 32-, 16-, and 8-bit data path
- 36-bit address
- 83.33MHz, maximum 333MB/s
• DCR
- 32-bit data path
- 10 bit address
On-Chip SRAM
Features include:
• Four banks of 64KB each for a total of 256KB
• Configurable as either Code (L2) cache or software-controlled on-chip memory, or SRAM
• Memory cycles supported:
- Single beat read and write, 1 to 16 bytes
- 32- and 64-byte burst transfers
- Guarded memory accesses
• Sustainable 2.6GB/s peak bandwidth at 166MHz
• Use as an L2 cache improves processor performance and reduces the PLB load
- Cache coherency maintained by a hardware snoop mechanism or software
- Data Array and Tag Array parity
- Unified data and instruction cache
- 4-way set associative
- 36-bit addressing
- Full LRU replacement algorithm
- Write through, look aside
• Use as Ethernet packet store allows Ethernet packets to be held for processing by the TAH unit
PCI-X Interface
The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory.
This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit PCI-X buses. PCI
32/64-bit conventional mode, compatible with PCI Version 2.3, is also supported.
Reference Specifications:
• PowerPC CoreConnect Bus (PLB) Specification Version 3.1
• PCI Specification Version 2.3
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• PCI-X 1.0a
- Split transactions
- Frequency to 133MHz
- 32- and 64-bit bus
• PCI 2.3 backward compatibility
- Frequency to 66MHz
- 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
• Support for Message Signaled Interrupts
AMCC
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
