440GX – Power PC 440GX Embedded Processor
Revision 1.15 – August 30, 2007
Data Sheet
PPC440GX Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Timers
MMU
63 internal
18 external
Power
Mgmt
DCRs
PPC440
Processor Core
JTAG
32KB
D-Cache
Trace
32KB
I-Cache
Arb
DCR Bus
GP
Timers
GPIO
IIC
x2
UART
x2
On-chip Peripheral Bus (OPB)
L2 Controller
SRAM
256KB
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
TAH
External
External
Bus Master
Bus
Controller Controller
83MHz max
32-bit addr
32-bit data
MAL
10/100
10/100/
x2
1000 x2
Ethernet
I2O
Messaging
PCI-X
Bridge
DDR SDRAM
Controller
RGMII
Bridge
1 GMII
or
2 RGMII
or
1 TBI
or
2 RTBI
ZMII
Bridge
1 MII
or
2 RMII
or
4 SMII
133MHz max 166MHz max
32/64-bit data 13-bit addr
32/64-bit data
The PPC440GX is designed using the IBM
®
Microelectronics Blue Logic
™
methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus
™
Architecture.
Note:
IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 200MHz
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GX processor through the use of
mtdcr
and
mfdcr
instructions.
6
AMCC