Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
I/O Timing—DDR SDRAM T
Notes:
and T
DIN
SIN
1. TSIN = Delay from DQS at package pin to C on Stage 1 FF.
2. TDIN = Delay from data at package pin to D on Stage 1 FF.
3. The time values for TSIN include 1/4 of a cycle at the indicated clock speed.
TSIN (ns)
minimum
TSIN (ns)
maximum
TDIN (ns)
minimum
TDIN (ns)
maximum
Clock Speed (MHz)
Signal Name
Signal Name
166
166
166
166
166
166
166
166
166
200
200
200
200
200
200
200
200
200
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
2.132
2.132
2.127
2.116
2.100
2.103
2.144
2.110
2.122
1.942
1.920
1.938
1.945
1.932
1.936
1.938
1.943
1.952
2.884
2.867
2.873
2.851
2.845
2.844
2.902
2.864
2.860
2.365
2.314
2.361
2.370
2.332
2.348
2.356
2.360
2.381
MemData00:07
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
0.779
0.789
0.779
0.791
0.766
0.754
0.747
0.770
0.759
0.638
0.631
0.634
0.624
0.630
0.619
0.635
0.642
0.641
1.502
1.521
1.530
1.553
1.501
1.525
1.513
1.521
1.464
1.165
1.149
1.151
1.169
1.151
1.133
1.149
1.151
1.141
MemData00:07
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
AMCC
85
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
