440GR – PPC440GR Embedded Processor
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
Table 2. DCR Address Map (4KB of Device Configuration Registers)
Function
Total DCR Address Space
1
By function:
Reserved
Clocking Power On Reset
System DCRs
Memory Controller
External Bus Controller
Reserved
PLB 128 Performance Monitor
Reserved
PLB 128 to PLB 64 Bridge Out
PLB 64 to PLB 128 Bridge In
Reserved
PLB 64 Arbiter
PLB 128 Arbiter
PLB 64 to OPB Bridge Out
Reserved
OPB to PLB 64 Bridge In
Power Management
Reserved
Interrupt Controller 0
Interrupt Controller 1
Clock, Control, and Reset
Reserved
DMA to PLB 64 Controller
Reserved
Ethernet MAL
Reserved
DMA to PLB 128 Controller
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register. One kiloword (1024W) equals 4KB (4096 B).
000
00C
00E
010
012
014
016
018
020
030
040
070
080
090
0A0
0A8
0B0
0B8
0C0
0D0
0E0
0F0
100
140
180
200
300
340
00B
00D
00F
011
013
015
017
01F
02F
03F
06F
08F
08F
09F
0A7
0AF
0B7
0BF
0CF
0DF
0EF
0FF
13F
17F
1FF
2FF
33F
3FF
12W
2W
2W
2W
2W
2W
2W
8W
16W
16W
64W
16W
16W
16W
8W
8W
8W
8W
16W
16W
16W
16W
64W
64W
128W
512W
64W
512W
Start Address
000
End Address
3FF
Size
1KW (4KB)
1
AMCC Proprietary
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
