Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 11. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
+1.4
Typical
+1.5
Maximum
+1.6
Unit
V
Notes
VDD
Logic Supply Voltage
I/O Supply Voltage
4
4
OVDD
SVDD
+3.0
+3.3
+3.6
V
SDRAM Supply Voltage
+2.3
+2.5
+2.7
V
4
AVDD
PLL Supply Voltages
+1.4
+1.5
+1.6
V
3, 4
3, 4
2
SAVDD
SVREF
SDRAM PLL Voltage
+1.4
+1.5
+1.6
V
DDR SDRAM Reference Voltage
Input Logic High (2.5V SSTL)
+1.15
+1.25
+1.35
SVDD+0.3
V
SVREF+0.18
V
Input Logic High (2.5V CMOS, 3.3V tolerant receiver)
Input Logic High (3.3V PCI)
1.7
???
V
VIH
0.5OVDD
OVDD+0.5
V
1
1
1
1
Input Logic High (3.3V LVTTL)
Input Logic Low (2.5V SSTL)
+2.0
-0.3
+3.6
V
SVREF-0.18
V
Input Logic Low (2.5V CMOS, 3.3V tolerant receiver)
Input Logic Low (3.3V PCI)
0.7
V
VIL
0.35OVDD
-0.5
0
V
Input Logic Low (3.3V LVTTL)
Output Logic High (2.5V SSTL)
Output Logic High (2.5V CMOS, 3.3V tolerant receiver)
Output Logic High (3.3V PCI)
+0.8
V
SVDD
+1.95
2.0
V
V
VOH
0.9OVDD
OVDD
OVDD
V
Output Logic High (3.3V LVTTL)
+2.4
0
V
V
V
V
V
Output Logic Low (2.5V SSTL)
0.55
0.4
Output Logic Low (2.5V CMOS, 3.3V tolerant receiver)
Output Logic Low (3.3V PCI)
VOL
0.1OVDD
Output Logic Low (3.3V LVTTL)
0
0
+0.4
0
IIL1
IIL2
Input Leakage Current (No pull-up or pull-down)
μA
μA
μA
V
Input Leakage Current for Pull-Down
0 (LPDL)
-150 (LPDL)
200 (MPUL)
0 (MPUL)
+3.9
IIL3
Input Leakage Current for Pull-Up
VIMAO
VIMAU
VOMAO
VOMAU3
Input Max Allowable Overshoot (3.3V LVTTL)
Input Max Allowable Undershoot (3.3V LVTTL)
Output Max Allowable Overshoot (3.3V LVTTL)
Output Max Allowable Undershoot (3.3V LVTTL)
4, 5
4, 5
4, 5
4, 5
-0.6
-0.6
V
+3.9
V
V
62
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
