Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Sheet 1 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
PCI Interface
Description
I/O
Type
Notes
PCIAD00:31
PCIC0:3/BE0:3
PCIClk
Address/Data bus (bidirectional).
I/O
I/O
I
3.3V PCI
3.3V PCI
3.3V PCI
PCI Command/Byte Enables.
Provides timing to the PCI interface for PCI transactions.
5
Indicates the driving device has decoded its address as the
target of the current access.
PCIDevSel
PCIFrame
I/O
I/O
O
3.3V PCI
3.3V PCI
3.3V PCI
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Driven by the current master to indicate beginning and
duration of an access.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is PCIGnt0. When
the internal arbiter is disabled, output is Req.
PCIGnt1/Req
PCIGnt2:6
PCIIDSel
PCIINT
Indicates that the specified agent is granted access to the bus.
O
I
3.3V PCI
3.3V PCI
3.3V PCI
Used as a chip select during configuration read and write
transactions.
Level sensitive PCI interrupt.
O
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
PCIIRDY
PCIPar
I/O
I/O
I/O
3.3V PCI
3.3V PCI
3.3V PCI
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Even parity.
Reports data parity errors during all PCI transactions except a
Special Cycle.
PCIPErr
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Indicates to the PCI arbiter that the specified agent wishes to
use the bus. When the internal arbiter is enabled, input is
PCIReq0. When internal arbiter is disabled, input is Gnt.
PCIReq0/Gnt
I
3.3V PCI
4
4
An indication to the PCI arbiter that the specified agent wishes
to use the bus.
PCIReq1:5
PCIReset
I
3.3V PCI
3.3V PCI
Brings PCI device registers and logic to a consistent state.
O
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
PCISErr
PCIStop
PCITRDY
I/O
I/O
I/O
3.3V PCI
3.3V PCI
3.3V PCI
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Indicates the current target is requesting the master to stop the
current transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
Indicates the target agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system)
AMCC Proprietary
53
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
