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PPC440GR-3JA667C 参数 Datasheet PDF下载

PPC440GR-3JA667C图片预览
型号: PPC440GR-3JA667C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 667MHz, CMOS, PBGA456, 35 MM, ROHS COMPLIANT, THERMALLY ENHANCED, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 82 页 / 1147 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.16 – July 19, 2006  
440GR – PPC440GR Embedded Processor  
Preliminary Data Sheet  
Example 1:  
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage  
1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically close  
to the PPC440GR, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary to  
sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to  
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, T is  
T
controlled and set by the software.  
Figure 11. DDR SDRAM Read Cycle Timing—Example 1  
DQS at pin  
Data at pin  
D0  
D1  
D3  
D2  
T
SIN  
DQS Stage 1 C  
Data in Stage 1 D  
D0  
D1  
D3  
D2  
T
DIN  
T
P
T
P
High  
Low  
D0  
D1  
D2  
D3  
Data out Stage 1  
D0  
D2  
High  
Low  
D0  
D1  
D2  
D3  
Data in at RDSP  
with no ECC  
D2  
D0  
T
T
PLB Clock  
High  
Low  
D0  
D1  
D2  
D3  
Data out RDSP  
(1)  
T
= Delay from DQS at package pin to C on Stage 1 FF.  
SIN  
T = Propagation delay through FFs  
P
T
= Delay from data at package pin to D on Stage 1 FF.  
DIN  
T = Propagation delay, Stage 1 input to RDSP input w/o ECC  
T
76  
AMCC Proprietary  
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