Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
NAND Flash Interface
NFALE
Description
I/O
Type
Notes
Address Latch Enable.
O
O
O
Multiplex
Multiplex
Multiplex
NFCE0:3
Chip Enable (multiplexed with the PerCS0:3 signals).
Command Latch Enable.
NFCLE
Ready/Busy.
NFRdyBusy
I
Multiplex
Indicates status of device during program erase or page read.
This signal is wire-or connected from all NAND Flash devices.
NFREn
Read Enable strobe.
Write Enable strobe.
O
O
Multiplex
Multiplex
NFWEn
Serial Peripheral Interface
Clock output.
SCPClkOut, the serial port master clock out, is used to
synchronize all data movement both into and out of the device
through the serial data ports. Normally, data is shifted out on
the rising edge of the clock and shifted in on the negative
edge.
SCPClkOut
O
3.3V LVTTL
SCPClkOut is also used to shift data into and out of the slave
device. When the SPMODE register is reset, SCPClkOut is
forced to 0.
Data In.
SCPDI
I
3.3V LVTTL
3.3V LVTTL
Data is received from the connected slave device and is
captured synchronously with SysClk.
Data output.
SCPDO
O
Data is sent to the connected slave device synchronously with
SysClk.
Interrupts Interface
IRQ0:4
External interrupt requests 0 through 4.
External interrupt request 5.
I/O
I
3.3V LVTTL
1, 5
1, 5
1, 5
3.3V tolerant
2.5V CMOS
IRQ5
IRQ6:9
External interrupt requests 6 through 9.
I/O
3.3V LVTTL
JTAG Interface
3.3V LVTTL
w/pull-up
TCK
Test Clock.
I
1
4
3.3V LVTTL
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V LVTTL
w/pull-up
1
5
3.3V LVTTL
w/pull-up
TRST
Test Reset.
I
AMCC Proprietary
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