Part Number 440GP
Revision 1.01 – November 1, 2004
Data Sheet
440GP
Power PC 440GP Embedded Processor
Features
®
interfaces. Operational modes supported are MII,
RMII, and SMII.
• PowerPC 440 processor core operating up to
500MHz with 32KB I- and D-caches
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• On-chip 8 KB SRAM
• Selectable processor:bus clock ratios of 3:1, 4:1,
5:1, 5:2, 7:2
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) 32/64-bit interface operating up to
133MHz
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• External Peripheral Bus for up to eight devices
with external mastering
• DMA support for external peripherals, internal
UART and memory
• Internal Processor Local Bus (PLB) runs at DDR
SDRAM interface frequency
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI V2.2
• Processor can boot from PCI memory
• Available in ceramic and plastic packages
• Two Ethernet 10/100Mbps half- or full-duplex
Description
Designed specifically to address high-end embedded
applications, the PowerPC 440GP (PPC440GP)
provides a high-performance, low power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation.
Technology: CMOS SA-27E, 0.18µm (0.11 L ), 5-
layer metal
eff
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA)
Power (estimated): Less than:
4.0W in normal mode
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,8KB SRAM,
PCI-X bus interface, Ethernet interfaces, control for
external ROM and peripherals, DMA with scatter-
gather support, serial ports, IIC interface, and general
purpose I/O.
1.0W in sleep mode
Supply voltages required: 3.3V, 2.5V, 1.8V
AMCC
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
