Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut0(0).
2. The TDS values in the table include 3/4 of a cycle at the indicated clock speed.
3. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle
time for the lower clock frequency (TDS - 5.625 + 0.75TCYC).
TDS (ns)
Clock Speed (MHz)
Signal Name
Minimum
Maximum
6.25
133
133
133
133
133
133
133
133
133
DQS0
na
na
na
na
na
na
na
na
na
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
6.25
6.25
6.25
6.25
6.25
6.25
6.25
6.25
I/O Timing—DDR SDRAM T , T , and T
SK SA
HA
Notes:
1. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).
2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and
subtract TSK maximum (0.75TCYC - TSKmax).
3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
TSK minimum (0.25TCYC + TSKmin).
TSK (ns)
TSA (ns)
THA (ns)
Clock Speed (MHz)
Signal Name
Minimum
0.4
Maximum
1.2
Minimum
4.425
4.425
4.425
4.425
4.425
4.425
4.425
Minimum
2.275
2.275
2.275
2.275
2.275
2.275
2.275
133
133
133
133
133
133
133
MemAddr00:12
BA0:1
0.4
1.2
BankSel0:3
ClkEn0:3
CAS
0.4
1.2
0.4
1.2
0.4
1.2
RAS
0.4
1.2
WE
0.4
1.2
AMCC
73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
