Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
- 133MHz, maximum 4.2GB/s (simultaneous read and write)
- Processor:bus clock ratios of 3:1, 4:1, 5:1, 5:2, and 7:2
• OPB
- Dynamic bus sizing 32-, 16-, and 8-bit data path
- Separate and simultaneous read and write data paths
- 36-bit address
- 66.66MHz, maximum 266MB/s
• DCR
- 32-bit data path
- 10 bit address
On-Chip SRAM
Features include:
• One physical bank of 8KB
• Memory cycles supported:
- Single beat read and write, 1 to 16 bytes
- 32- and 64-byte burst transfers
- Guarded memory accesses
• Sustainable 2.1GB/s peak bandwidth at 133MHz
PCI-X Interface
The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory.
This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit PCI-X buses. PCI
32/64-bit conventional mode, compatible with PCI Version 2.2, is also supported.
Reference Specifications:
• PowerPC CoreConnect Bus (PLB) version PLB4
• PCI Specification Version 2.2
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• PCI-X 1.0a
- Split transactions
- Frequency to 133MHz
- 32- and 64-bit bus
• PCI 2.2 backward compatibility
- Frequency to 66MHz
- 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
• Support for Message Signaled Interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
AMCC
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
