Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—400, 466, and 500MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
Setup
Signal
Clock
Notes
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Time
(TIS min)
External Slave Peripheral Interface
PerData00:31
PerAddr00:31
PerPar0:3
3
3
1
1
9
7.6
8.4
6.5
6
0
0
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
na
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
4
1
0
PerWBE0:3
PerCS0:7
2.5
na
na
na
2.5
5
1
0
na
na
na
1
0
PerOE
6
0
PerWE
7
0
PerBLast
5
na
na
na
na
0
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerReady[RcvrInh]
PerR/W
1
na
5.6
na
7
2.5
dc
na
dc
1
15.3
na
10.2
na
DMAReq0:3
DMAAck0:3
EOT0:3/TC0:3
dc
na
dc
15.3
15.3
10.2
10.2
6.8
0
External Master Peripheral Interface
PerClk
na
na
na
na
1
na
6.2
na
na
0
15.3
15.3
na
10.2
10.2
na
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
3.5
na
na
0
na
1
6.4
na
15.3
na
10.2
na
2.5
na
na
0
na
na
1
6.2
6.2
na
15.3
15.3
15.3
10.2
10.2
10.2
BusReq
PerErr
na
0
4.5
na
AMCC
69
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
