Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. Again, T = 1.5ns and T
=
T
TE
4.3ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 3
DQS at pin
Data at pin
D0
D1
D3
D2
T
SIN
DQS Stage 1 C
Data in Stage 1 D
D0
D1
D3
D2
T
DIN
T
P
High
Low
D0
D1
D2
D3
Data out Stage 1
D0
D2
PLB Clock
Read Clock Delayed
T
P
D0
D1
High
D2
D3
Data out Stage 2
Low
High
Low
D2
D3
D0
D1
Data out Stage 3
with ECC
T
TE
High
Low
D0
D1
D2
D3
Data in at RDSP
with ECC
High
Low
D0
D1
D2
D3
Data out RDSP
with ECC
(3)
T = Propagation delay from Stage 2 input to RDSP input w/o ECC
T
T
= Propagation delay from Stage 2 input to RDSP input with ECC
TE
AMCC
79
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
