Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
MemClkOut0(0)
T
MD
T
min = 850ps
MD
T
max =
2600ps
MD
Read Clock
T
RD
T
min =
0ps
RD
T
max =
300ps
RD
In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
Mux
RDSP
FF
Package pins
Q
D
PLB bus
ECC
Stage 3
Stage 1
Stage 2
Q
D
Q
D
D
Q
C
FF,
XL
FF
FF
Data
C
C
C
Read Select
(SDRAM0_TR1)
1/4
Cycle
Delay
Programmed
Read Clock
Delay
DQS
PLB Clock
FF Timing:
T
T
T
= Input setup time = 0.2ns
= Input hold time = 0.1ns
= Propagation delay (D to Q or C to Q) =
FF: Flip-Flop
XL: Transparent Latch
IS
IH
0.6ns maximum
P
AMCC
75
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
