Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 5 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
UART1_RTS/DTR
Description
I/O
Type
Notes
UART1 Request To Send or Data Terminal Ready. The choice is
determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
I/O
1, 4
IIC Peripheral Interface
5V tolerant
IIC0SClk
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
I/O
I/O
I/O
I/O
1, 2
1, 2
1, 2
1, 2
3.3V LVTTL
5V tolerant
3.3V LVTTL
IIC0SDA
IIC1SClk
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
IIC1SDA
Interrupts Interface
IRQ00:10
5V tolerant
External interrupt Requests 0 through 10.
External interrupt Requests 11 through 12.
I
I
1, 5
3.3V LVTTL
IRQ11:12
3.3V PCI
JTAG Interface
3.3V CMOS
w/pull-up
TCK
Test Clock.
I
1
4
3.3V CMOS
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V CMOS
w/pull-up
1
5
Test Reset. During chip power-up, this signal must be low from the
start of VDD ramp-up until at least 16 SysClk cycles after VDD is
stable in order to initialize the JTAG controller.
3.3V CMOS
w/pull-up
TRST
I
52
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
