Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Power Sequencing
Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete
(OV and V are below +0.4V) before a new power-up cycle is started.
DD
DD
Analog Voltage Filter
The analog voltages (AVdd, EAVdd, and UnAVdd) used for the on-chip PLLs can be derived from the logic voltage, but must be
filtered before the PPC440EPx. A Separate filter, as shown below, is recommended for each voltage.
• The filter should keep the analog voltage to analog ground compression/expansion due to noise less than +50
mV.
• Keep all wire lengths as short as possible.
• Analog grounds must be brought out and connected to the digital ground plane at the filter capacitor.
• The impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where
noise is expected.
VDD
AVDD, EAVDD, UnAVdd
L
L – SMT ferrite bead chip, Murata
BLM21PG600SN1
C
C – 0.1μF ceramic dielectric
AGND, EAGND, UnAGND
GND
Power Specification
The following tables contain measured power numbers. The measurement conditions are listed as Notes below
each table.
Table 12. Typical DC Power Supply Requirements Using DDR2 Memory
+1.5V Supply
(VDD+AVDD+EAVDD
+1.8V Supply
+2.5V Supply
+3.3V Supply
(OVDD+UAVDD)
Frequency (MHz)
Total
Unit
Notes
)
(SOVDD
)
(EOVDD
)
400
533
1.61
1.82
2.16
0.35
0.36
0.37
0.28
0.28
0.28
0.2
0.2
0.2
2.44
2.66
3.01
W
W
W
1
1
1
667
Notes:
1. Typical power is measured and is based on a nominal voltage of VDD = +1.5V, TC = 100°C, while running Linux and a test application
that exercises each function with representative traffic.
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