Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Table 27. I/O Timing—DDR SDRAM T and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 166MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (6ns x 0.25 = 1.5 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, TSD − 1.5 + 0.25TCYC).
TSD (ns)
THD (ns)
Signal Names
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
Reference Signal
DQS0
1.37
1.41
1.40
1.41
1.45
1.40
1.46
1.45
1.46
1.23
1.18
1.17
1.20
1.18
1.18
1.17
1.10
1.18
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
AppliedMicro Proprietary
89