440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
Block Diagram
Figure 2. PPC440EPx Functional Block Diagram
10
External
Interrupts
Clock
Control,
Reset
Timers
MMU
UIC
PPC440
Processor
FPU
JTAG
32KB
D-Cache
Security
(optional)
Trace
32KB
I-Cache
SRAM
16KB
PLB (PLB4—128 bits)
PLB-PLB
Bridges
PLB (PLB3—64 bits)
DCR Bus
External
Peripheral
Controller
NAND
Flash
Controller
PCI
Bridge
Power
Mgmt
DCRs
83MHz max
- 30-bit addr
- 32/16-bit data
66MHz max
- 32 bits
- 6 devices
OPB OPB OPB
DMA
Controller Bridge Bridge Bridge
DDR2/1
SDRAM
Controller
333MHz max
data rate
- 14-bit addr
- 64/32-bit data
OPB
Bridge
DMA
Controller
GPT
OPB 1
OPB 2
On-chip Peripheral Bus (OPB 0)
Device
Host
MAL
USB 2.0
Ethernet
10/100/1000
x2
ZMII
RGMII
GPIO
SPI
IIC
x2
BSC
UART
x4
2.0 PHY
D+/D−
The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect Bus
™
Architecture.
Address Maps
The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map.
This address map defines the possible contents of various address regions which the processor can access. The
second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440EPx processor through the use of
mtdcr
and
mfdcr
instructions.
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
