Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Table 8. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
DDR2/1 SDRAM Interface
2.5V (1.8V)
SDRAM-DDR
BA0:2
Bank Address supporting up to eight internal banks.
Selects up to two external DDR SDRAM banks.
Column Address Strobe.
O
O
O
O
O
2.5V (1.8V)
SDRAM-DDR
BankSel0:1
CAS
2.5V (1.8V)
SDRAM-DDR
2.5V (1.8V)
SDRAM-DDR
ClkEn
Clock Enable.
DM0:7
DM8
Memory write data byte lane masks. DM8 is the byte lane mask
for the ECC byte lane.
2.5V (1.8V)
SDRAM-DDR
DQS0:7
DQS8
Byte lane data strobe.
2.5V (1.8V)
SDRAM-DDR
I/O
I/O
O
Byte lane data strobe for ECC.
2.5V (1.8V)
SDRAM-DDR
ECC0:7
ECC check bits 0:7.
2.5V (1.8V)
SDRAM-DDR
MemAddr00:13
MemData00:63
Memory address bus.
2.5V (1.8V)
SDRAM-DDR
Memory data bus (MemData32:63 available for DDR2 only).
I/O
2.5V (1.8V)
SDRAM-DDR
Diff driver
MemClkOut
MemClkOut
Subsystem clock.
O
2.5V (1.8V)
SDRAM-DDR
MemODT0:1
RAS
DDR2 On-die termination enable (not used with DDR1).
Row Address Strobe.
O
O
O
I
2.5V (1.8V)
SDRAM-DDR
2.5V (1.8V)
SDRAM-DDR
WE
Write Enable.
Volt ref receiver
(1.25V or 0.9V)
SVREF1A:B
SVREF2A:B
DDR SDRAM reference voltage 1 input.
DDR SDRAM reference voltage 2 input.
Volt ref driver
(1.25V or 0.9V)
I
58
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
