Revision 1.25 – December 18, 2006
440EP – PPC440EP Embedded Processor
DDR SDRAM Write Operation
Data Sheet
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 8. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut0
MemClkOut0(90)
T
SA
Addr/Cmd
T
DS
T
T
SK
DS
T
HA
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
= Setup time for address and command signals to MemClkOut0(90)
SK
T
SA
T
T
T
T
= Hold time for address and command signals from MemClkOut0(90)
HA
SD
HD
DS
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
AMCC Proprietary
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