Revision 1.25 – December 18, 2006
440EP – PPC440EP Embedded Processor
Data Sheet
Table 16. I/O Specifications—All Speeds (Sheet 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
Ethernet SMII Interface
EMC0RxD
1.5
n/a
1.5
n/a
n/a
1
n/a
3.5
n/a
3.5
n/a
n/a
0
5.1
5.1
5.1
5.1
5.1
6.8
6.8
6.8
6.8
6.8
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
1
EMC0TxD
n/a
1
1
EMC1RxD
n/a
0
1
1
EMC1TxD
n/a
n/a
EMCRefClk
n/a
1, async
Internal Peripheral Interface
IIC0SClk
n/a
n/a
n/a
n/a
5
5
0
0
15.3
15.3
15.3
15.3
15.3
15.3
15.3
n/a
10.2
10.2
10.2
10.2
10.2
10.2
10.2
n/a
IIC0SData
IIC1SClk
IIC1SData
SCPClkOut
SCPDI
7
2
6
n/a
6
0
n/a
0
7
2
SCPDO
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
7
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0.05
n/a
0.02
n/a
0.05
n/a
n/a
n/a
n/a
0.1
n/a
n/a
UARTSerClk
UARTn_Rx
UARTn_Tx
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0
n/a
n/a
10.3
n/a
7.1
UARTn_DCD
UARTn_DSR
UARTn_CTS
UARTn_DTR
UARTn_RI
n/a
n/a
n/a
na
na
10.3
n/a
7.1
n/a
UARTn_RTS
USB1Clk
10.3
n/a
7.1
n/a
USB1DevXcvr
USB1DevXcvr
USB1HostXcvr
USB1HostXcvr
USB2Clk
USB 1.1
USB 1.1
USB 1.1
USB 1.1
n/a
USB 1.1
USB 1.1
USB 1.1
USB 1.1
n/a
3
0
3
0
3
0
n/a
n/a
3
n/a
n/a
0
USB2DI0:7
n/a
n/a
USB2DO0:7
USB2LS0:1
USB2OM0:1
USB2RxAct
USB2RxDV
USB2RxErr
USB2Susp
n/a
5.2
n/a
7
5.1
6.8
n/a
3
n/a
0
n/a
n/a
7.1
9.6
n/a
3
n/a
0
n/a
n/a
n/a
n/a
n/a
n/a
6
7.1
9.6
3
0
7.1
9.6
3
0
7.1
9.6
USB2TermSel
USB2TxRdy
USB2TxVal
USB2XcvrSel
Interrupts Interface
IRQ0:9
3
0
7.1
9.6
n/a
3
n/a
0
n/a
n/a
n/a
n/a
7.1
9.6
3
0
7.1
9.6
n/a
n/a
n/a
n/a
n/a
n/a
70
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
