Revision 1.29 – May 07, 2008
440EP – PPC440EP Embedded Processor
Data Sheet
Table 8. Signal Functional Description (Sheet 7 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
NAND Flash Interface
NFALE
Description
I/O
Type
Notes
Address Latch Enable.
O
O
O
Multiplex
Multiplex
Multiplex
NFCE0:3
Chip Enable (multiplexed with the PerCS0:3 signals).
Command Latch Enable.
NFCLE
Ready/Busy.
NFRdyBusy
I
Multiplex
Indicates status of device during program erase or page read. This
signal is wire-or connected from all NAND Flash devices.
NFREn
Read Enable strobe.
Write Enable strobe.
O
O
Multiplex
Multiplex
NFWEn
Serial Peripheral Interface
SCPClkOut
SCPDI
Clock output.
Data In.
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
2
2
2
SCPDO
Data output.
O
Interrupts Interface
IRQ0:4
External interrupt requests 0 through 4.
External interrupt request 5.
I/O
I
3.3V LVTTL
1
1
1
3.3V tolerant
2.5V CMOS
IRQ5
IRQ6:9
External interrupt requests 6 through 9.
I/O
3.3V LVTTL
JTAG Interface
3.3V LVTTL
w/pull-up
TCK
Test Clock.
I
1
4
3.3V LVTTL
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
Test Reset.
3.3V LVTTL
3.3V LVTTL
w/pull-up
1
5
3.3V LVTTL
w/pull-up
Note: Must be asserted low during a power-on system reset in
order to reset the JTAG interface. If the JTAG interface is not reset,
the processor may not boot.
TRST
I
58
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
