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PPC405EP-3LB333CZ 参数 Datasheet PDF下载

PPC405EP-3LB333CZ图片预览
型号: PPC405EP-3LB333CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405EP的PowerPC嵌入式处理器 [PowerPC 405EP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 50 页 / 805 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – September 10, 2007  
PPC405EP – PowerPC 405EP Embedded Processor  
Initialization  
Data Sheet  
The following describes the method by which initial chip settings are established when a system reset occurs.  
Strapping  
When the SysReset input is driven low (system reset), the state of certain I/O pins is read to enable default initial  
conditions prior to PPC405EP start-up. The actual capture instant is the nearest system clock edge before the  
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)  
resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to +5V. The  
recommended pull-down is 1KΩ to GND. These pins are use for strap functions only during reset. They are used  
for other signals during normal operation. The following table lists the strapping pins along with their functions and  
strapping options. The signal names assigned to the pins for normal operation appear below the pin number.  
Table 16. Strapping Pin Assignments  
Function  
Option  
Ball Strapping  
P04  
IIC EEPROM controller  
UART0_Tx  
If the controller is enabled, 32 bytes of configuration data  
are read from the EEPROM.  
Disable  
Enable  
0
1
EEPROM address (P04 = 1)  
or  
Boot ROM width (P04 = 0)  
N02  
UART0_RTS  
Y17  
SysErr  
When P04 = 1, these pins set the high-order two  
bits of the EEPROM base address.  
High order EEPROM base address bits  
Address bit  
Address bit  
8 bits  
0
0
1
1
0
1
0
1
When P04 = 0, these pins indicated the width of  
the boot ROM.  
16 bits  
reserved  
reserved  
EEPROM  
During reset, configuration values other than the internal default values can be read from a serial EEPROM  
connected to the IIC port. The association of bits in the EEPROM with the configuration values and their default  
values are covered in detail in the PowerPC 405EP Embedded Processor User’s Manual.  
Note: If P04 is strapped to 1, and the EEPROM is not connected or is defective, the PPC405EP remains in the  
reset state and will not boot.  
48  
AMCC  
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