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PPC405EP-3LB333CZ 参数 Datasheet PDF下载

PPC405EP-3LB333CZ图片预览
型号: PPC405EP-3LB333CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405EP的PowerPC嵌入式处理器 [PowerPC 405EP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 50 页 / 805 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – September 10, 2007  
PPC405EP – PowerPC 405EP Embedded Processor  
Data Sheet  
Table 6. Signal Functional Description (Sheet 2 of 6)  
Secondary multiplexed signals are shown in brackets.  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.  
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Bus Control Signals” on page 30.  
Signal Name  
Description  
I/O  
Type  
Notes  
5V tolerant  
3.3V PCI  
PCIReq1:2  
PCIReq input when internal arbiter is used.  
I
Gnt0 when internal arbiter is used  
or  
5V tolerant  
3.3V PCI  
PCIGnt0/Req  
O
O
Req when external arbiter is used.  
5V tolerant  
3.3V PCI  
PCIGnt1:2  
Ethernet Interface  
PHY0Rx0:1D3:0  
PCIGnt output when internal arbiter is used.  
Received data. This is a nibble wide bus from the PHY. The data is  
synchronous with the PHY0RxClk.  
5V tolerant  
3.3V LVTTL  
I
O
I
1
Transmit data. A nibble wide data bus towards the net. The data is  
synchronous to the PHY0TxClk.  
5V tolerant  
3.3V LVTTL  
EMC0Tx0:1D3:0  
PHY0Rx0:1Err  
Receive Error. This signal comes from the PHY and is synchronous to  
the PHY0RxClk.  
5V tolerant  
3.3V LVTTL  
1
1
Receive Medium clock. This signal is generated by the PHY. If an  
EMAC interface is not used, this clock must be present in order to  
reset the EMAC.  
5V tolerant  
3.3V LVTTL  
PHY0Rx0:1Clk  
I
Receive Data Valid. Data on the Data Bus is valid when this signal is  
activated. Deassertion of this signal indicates end of the frame  
reception.  
5V tolerant  
3.3V LVTTL  
PHY0Rx0:1DV  
PHY0CrS0:1  
I
I
1
1
5V tolerant  
3.3V LVTTL  
Carrier Sense signal from the PHY. This is an asynchronous signal.  
Transmit Error. This signal is generated by the Ethernet controller, is  
connected to the PHY and is synchronous with the PHYTxClk. It  
informs the PHY that an error was detected.  
5V tolerant  
3.3V LVTTL  
EMC0Tx0:1Err  
O
Transmit Enable. This signal is driven by the EMAC to the PHY. Data  
is valid during the active state of this signal. Deassertion of this signal  
indicates end of frame transmission. This signal is synchronous to the  
PHY0TxClk.  
5V tolerant  
3.3V LVTTL  
EMC0Tx0:1En  
O
This clock comes from the PHY and is the Medium Transmit clock. If  
an EMAC interface is not used, this clock must be present in order to  
reset the EMAC.  
5V tolerant  
3.3V LVTTL  
PHY0Tx0:1Clk  
PHY0Col0:1  
EMC0MDClk  
I
I
1
1
5V tolerant  
3.3V LVTTL  
Collision signal from the PHY. This is an asynchronous signal.  
Management Data Clock. The MDClk is sourced to the PHY.  
Management information is transferred synchronously with respect to  
this clock.  
5V tolerant  
3.3V LVTTL  
O
Management Data Input/Output is a bidirectional signal between the  
Ethernet controller and the PHY. It is used to transfer control and  
status information.  
5V tolerant  
3.3V LVTTL  
EMC0MDIO  
I/O  
1
32  
AMCC  
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