Revision 1.07 – September 10, 2007
Data Sheet
Figure 1. PPC405EP Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Timers
MMU
OCM
SRAM
Power
Mgmt
DOCM
IOCM
Event
Counters
OCM
Control
DCRs
UART
x2
PPC405
Processor Core
JTAG
16KB
D-Cache
DCU
Trace
ICU
DCR Bus
GPIO
IIC
GPT
16KB
I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
MAL
Ethernet
x2
Arb
Processor Local Bus (PLB)
SDRAM
Controller
External
Bus
Controller
29-bit addr
16-bit data
PCI Bridge
13-bit addr
32-bit data
66 MHz max (async)
MII
The PPC405EP is designed using the IBM Microelectronics Blue Logic
TM
methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect
TM
Bus Architecture.
AMCC
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
