欢迎访问ic37.com |
会员登录 免费注册
发布采购

PPC405EP-3LB133CZ 参数 Datasheet PDF下载

PPC405EP-3LB133CZ图片预览
型号: PPC405EP-3LB133CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405EP的PowerPC嵌入式处理器 [PowerPC 405EP Embedded Processor]
分类和应用: PC
文件页数/大小: 50 页 / 805 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第26页浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第27页浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第28页浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第29页浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第31页浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第32页浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第33页浏览型号PPC405EP-3LB133CZ的Datasheet PDF文件第34页  
Revision 1.07 – September 10, 2007  
PPC405EP – PowerPC 405EP Embedded Processor  
Data Sheet  
Unused I/Os  
Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pull-  
up and pull-down terminations as specified in the “Signal Functional Description” on page 31, good design practice  
is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM,  
and PCI buses should be configured and terminated as follows:  
Peripheral interface—PerAddr03:31, PerData00:15, and all of the control signals are driven by default. Pull  
up PerReady.  
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405EP  
to actively drive all of the SDRAM address, data, and control signals.  
PCI—The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI  
interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and  
actively drive PCIAD31:00, PCIC3:0/BE3:0, and the remaining PCI control signals by doing the following:  
- Strap the PPC405EP to disable the internal PCI arbiter.  
- Individually pull up PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V.  
- Pull up PCIReq1:2 through a 3.3kΩ resistor to +3.3V.  
- Pull down PCIReq0/Gnt through a 1kΩ resistor to GND.  
External Bus Control Signals  
All peripheral bus control signals (PerCS0:4, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the high-  
impedance state when ExtReset = 0. In addition, as detailed in the PowerPC 405EP Embedded Processor User’s  
Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals  
between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven  
state may affect any devices receiving that particular signal.  
The following table lists all of the I/O signals provided by the PPC405EP. Please refer to “Signals Listed  
Alphabetically” on page 13 for the pin number to which each signal is assigned.  
30  
AMCC  
 复制成功!